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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Miscellaneous I/O Speci ? cations
Table 19. Miscellaneous Inputs
DC Voltage Levels
Rise/Fall Time
Setup
Hold
Ref.
Edge
Time
Time Min.
Internal
Signal Name
V IL Max.
V IH Min.
Min. (ns) Max. (ns)
Clock
(+/-)
Min. (ns)
(ns)
Pullup
reset_n*
0.8
2.0
2
2
asynch
na
na
na
no
pwrup_init_en
1
0.8
2.0
2
2
asynch
na
na
na
no
inj_err_n 1
0.8
2.0
2
2
asynch
na
na
na
no
1. External pull-up required.
Clocking Strategies
The general XGXS clocking strategy is discussed in this section. As noted earlier, slip buffers are implemented in
both the transmit and receive paths to accommodate for timing differences between the clock domain associated
with the SERDES blocks and the clock domain for the XGMII interface.
XGMII Clocks
There are two clocks associated with the XGMII interface.
xgmii_rxclk_156
xgmii_rxclk_156 is a 156.25MHz reference clock used to clock all internal registers in the XGXS receive path. It is
also used to generate the xgmii_rxclk_156_out output clock from the XGMII interface. The XGMII outputs,
xgmii_rx_data[31:0] and xgmii_rx_crtl[3:0], are synchronous to xgmii_rxclk_156_out.
xgmii_txclk_156
xgmii_txclk_156 is a 156.25MHz clock input for the XGMII interface. The XGMII inputs, xgmii_tx_data[31:0] and
xgmii_tx_ctrl[3:0], are synchronous to this clock. A slip buffer compensates for the differences in the
xgmii_txclk_156 clock domain and the internal XAUI-based 156.25MHz clock domain.
XGMII timing was shown previously.
Embedded Core Clocks
There are several clocks associated with the interface to the SERDES block. Only SERDES block B is currently
used by the XGXS IP core. Figure 17 and Figure 18 show the transmit and receive interfaces between the FPSC
FPGA core and the embedded core. Only the clock related signals are discussed here. For additional discussion,
see the ORT82G5 Data Sheet.
30
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